1. Field of the Invention
The present invention relates to a potential difference transmission device and a semiconductor memory device such as a static random access memory (SRAM) using such a potential difference transmission device. In particular, the present invention relates to a semiconductor memory device to which a pipeline technique is applied.
2. Description of the Related Art
A pipeline technique is widely employed in the logic LSI of microprocessors and the like so as to increase the operation speed. For example, Japanese Patent Publication No. 64-35794 describes that the pipeline technique is applied to a memory so as to realize memory capable of operating at high speeds. This patent publication describes a random access memory which employs pipelining, in which a latch circuit temporarily storing 1 bit of information is provided between an address decoder and a memory cell array.
In the configuration as described above, all signal amplitudes in the memory are set to be equal to a full amplitude of the CMOS. As a result, the operation time of the latch circuit is prolonged. Consequently, the latch circuit significantly obstructs reduction of the cycle time. Moreover, in the case where the pipeline operation is realized by using a latch or a register during a time period from the input of an address decoder to the output of a sense amplifier, the processing performed in a memory cell array, that is, the processing from activation of a word line to validation of an output of the sense amplifier cannot be divided into a plurality of steps. The memory cycle time in the memory system employing the pipelining is dependent on the processing time of the stage requiring the longest processing time. The necessary time periods of the respective pipelined stages are compared with each other. As a result, it is found that the aforementioned undividable processing stage in the memory cell array requires the longest time period among all stages and thus determines the total cycle time. Therefore, if the stage in the memory cell array cannot be carried out at increased speed, a pipeline RAM having reduced cycle time cannot be realized by pipelining the processing.
An ideal pipelined processor decodes one instruction during each machine cycle. In order to maintain this speed, it is necessary to supply instructions and data via the pipeline at least at the rate of decoding by the processor. The stages of the pipeline are synchronized normally by using a clock. In order to assure data transmission throughout the pipeline processing, the clock is required to have a speed suitable for the latest transmission path. In the system including the pipeline memory, the access stage of the memory is one of the longest delay paths. Therefore, the speed at which the data is supplied from the pipeline memory determines the total speed of the pipeline processor system. Accordingly, in order to improve the system performance, it is essential to improve the speed of the pipeline memory.